Field of the Invention
The invention relates to a stacked semiconductor arrangement with an ESD protection circuit (ESD=electrostatic discharge).
Brief Description of the Related Art
Electrostatic discharge is a spark or a flashover occurring, for example, in an electronic circuit due to a large potential difference between two electronic components of the electronic circuit. The electrostatic discharge causes a very fast, very high electric voltage peak on an electronic component. This voltage peak can damage the electronic component. In particular in microelectronic circuits, the damage to the electronic components can be very large and lead to the functional failure of the microelectronic components. Particularly in semiconductor integrated circuits, the electrostatic discharge is one of the most frequent reasons for a malfunction of the semiconductor electronic circuit, and therefore numerous attempts have been made to counteract this problem.
For example, the European patent application no. EP 1 363 329 A2 (Micronas GmbH) teaches a protection structure against an electrostatic discharge using an MOS transistor.
A different solution for an ESD protection circuit is known, for example, from the US patent application no. US 2013/0070376 A1 (Semiconductor Manufacturing International (Beijing) Corporation). This ESD protection circuit of this patent application comprises a discharge path on the semiconductor chip. The discharge path comprises a plurality of MOS transistors connected in series between the ground line and the supply line. An ESD detection unit is connected to the gate of the MOS transistors and switches on the MOS transistors upon detecting an electrostatic discharge.
The U.S. Patent Application Publication No. 2010/0006943 discloses also an ESD protection circuit with a MOS transistor that is switched on upon occurrence of an electrostatic discharge.
From the U.S. Patent Application Publication No. 2010/0127359 A1, an ESD protection circuit is known, which can be removed after completion of the semiconductor chip. This ESD protection circuit comprises two diodes connected to ground.
The use of an ESD protection circuit in so-called dual-dies (two semiconductor chips) can provide a separate ESD protection circuit for each one of the semiconductor chips. In some cases, however, the two semiconductor chips need to be mutually isolated from one another, and in this case, upon an electrostatic discharge, there is no predefined current path between the connector on a first semiconductor chip and a further connector on the second semiconductor chip. A very large voltage can be caused thereby in the semiconductor arrangement with the two semiconductor chips. Thus, in such a case, a breakdown of the dielectric and damage of one or more of the electronic components in an integrated circuit on the semiconductor chip must be expected. The level at which the voltage breaks down is not predefined, and, as a result, the breakdown voltage is not predictable. Consequently, an ESD circuit is required for the protection of a semiconductor arrangement with several semiconductor chips to prevent the occurrence of an electrostatic discharge.